Top American memory maker Micron and FPGA maestro Xilinx have publicly demoed the first working RLDRAM 3 and memory controller setup, allowing logic-board manufacturers to begin implementing the memory standard.
The demo involved a Xilinx Virtex 7 FPGA interfacing with Micron’s RLDRAM 3 module array. The test system delivered 60 percent higher throughput on networking applications – over previous generation tech – and operates at speeds of up to 800 MHz (1.6 Mbps). It also offers a lower power envelope and more flexible memory configurations.
Micron developed RLDRAM together with the now-defunct memory division of Infineon, almost 13 years ago. Its main purpose was to create a memory with faster response times in random access, something standard DRAM has evolved very little over the course of the years.
RLDRAM 3 has the advantage of being six times faster than standard DDR3 SDRAM in terms of random access reads and is in itself all about low latencies, fast turn-around and cache speed to improve overall system responsiveness.
RLDRAM 3 is expertly positioned into the whole ‘caching’ business, which allows for all sorts of performance enhancements in just about any processing background. While this may seem a small demonstration for the duo, the fact remains that this is one of those ‘enabler’ technologies that will allow deep-pocket companies to invest heavily with a quick return on their investment. It is seen as a must-have technology for upcoming 40Gb and 100Gb networks. In this particular case, Micron and Xilinx have already signed-up Alcatel-Lucent who will use the tech as the foundation for their future 400Gb infrastructure.
RLDRAM 3 has numerous practical applications other than networking. According to Micron, just about any system can benefit from caching data, ie: CPU to high-performance graphics products that require speedy random access to largish texture data.
The joint Micron-Xilinx tech will benefit telecom carriers the most, who are pushing infrastructure bandwidth capacity hard before everything goes IP. Let’s face it, bandwidth is a measure of just how strong your business is.
Other partners include some high-fliers like Altera, Broadcom, Cavium, LSI Logic – which should provide an interesting complement for its newly bought SandForce controllers – and Tilera, the developers of the famous 64- and 100- core CPU.
Cracking the encryption used in embedded systems chips is nothing to worry about, says one of the biggest makers of chips of that type. .
Xilinx makes Field Programmable Gate Array (FPGA) chips for the US defence industry and claims it was not surprised when its products were hacked by a team of German researchers.
A company spokesman told GCN magazine it was aware of the hack for some years but also knew that the encryption protecting the configuration bitstream that provides instructions to the FPGA when it is powered up is only one layer of the chip’s security, he said.
The aerospace and defence industries who buy the chips know about the security problems in the hardware they use and implement their own cunning plans, he said,
He claimed that this was “a feature” that companies liked. It allowed users to set up their own defenses and allows greater flexibility in how the chips are used.
Xilinx, whose co-founders invented the first commercially viable FPGAs in 1985, has about half of the market.
FPGA was cracked by boffins at the Horst Gortz Institute for IT-Security at Ruhr University.
They were able to extract the key used to decrypt data in two models of FPGAs made by Xilinx using differential power analysis (DPA). This is a side-channel attack that looks at the the power consumption of the chip during the decryption process.
Looking at this they could extract the 256-bit Advanced Encryption Standard decryption keys from chips and decode it all in six hours.
Xilinx pointed out that it was really hard to mount an attack using this method as there were all sorts of barriers to entry.
Researchers at the University of California, San Diego have found that erasing sensitive data stored on Solid State hard drives (SSD’s) may not be as easy or reliable as they thought.
Two PhD students at the University’s Non-Volatile Systems Laboratory have presented research at this month’s USENIX Conference on File Storage Technologies that show even on-device secure erase commands may be buggy – and ineffective at removing sensitive data that may be stored on the SSD.
The researchers used a FPGA-based flash hardware tester named Ming the Merciless to analyse the data left on the SSD’s raw NAND flash chips, which are used to do the actual storage, and bypass any software built into the SSD’s interface.
They found that the build-in commands to delete all the data off an SSD disk are often reliable, but manufacturers have built versions with bugs causing them to work incorrectly.
Existing tools used to erase normal hard disks are entirely ineffective at destroying the data on SSDs. The final option for removing data from SSDs is to use dedicated software to overwrite parts of the device. These were found to be effective after 2 passes on the disk but not entirely reliable.
The researchers have published their paper online (or check out the synopsis). Also check out this YouTube videoshowing how they rounded off destroying the UK ID Card Database earlier this month.
Texas Memory Systems has launched the FC-381 8Gb Fibre Channel interface, which will double the bandwidth for its RamSan 630 Flash storage device.
The 8Gb Fibre Channel offers support for host bus adapters (HBA), Point-to-Point, Switched Fabric, Arbitrated Loop topologies, LUN masking and SNMP unit management. Along with full FC HBA support it should work with all switches and virtualisation devices.
The RamSan 630 itself offers 10 independent 8Gb FC ports, significantly more than a traditional RAID system. It also offers 10TB of Flash-based storage in a 3U rack-mounted enclosure.
The FC-381 is not the only high-performance connection option for the RamSan 630, as the IB-381 QDR InfiniBand interface will also be available, with speeds of up to 10Gb/s.
The RamSan 630 can accept five interfaces of either the FC or IB variety, each of which features an embedded 1GHz processor, a dedicated FPGA, and 128MB of flow control memory.
Texas Memory claims that the new interface can eliminate storage Input/Output bottlenecks and improve overall speed and performance of time critical applications.
Altera has revealed its latest product portfolio of 28 nanometer devices, which employ advances in transceiver technology, product architecture, IP integration and process technology.
The portfolio includes the Cyclone V FPGA, Arria V FPGA, Stratrix V FPGA, and HardCopy V ASIC ranges.
Cyclone V FPGA is a low power range aimed at applications for motor control, displays and software-defined radios. The range features 40 percent lower power costs than older models, along with 12 transceivers with speeds of up to 5Gb/s. PCIe Gen2 x1 blocks and memory controller suppoirt for LPDDR2, mobile DDR and DDR3 external memory is also included.
The Arria V FPGA range is aimed at low power devices, such as remote radio units, in-stuido mixers and 10G/40G linecards. This range offers 40 percent lower power costs compared to previous models and allow speeds of up to 10Gb/s. There’s also hard memory controller support for DDR3 external RAM and FIR filters with variable-precision DSP blocks.
The Stratix V FPGA range is aimed at high-bandwidth applications, including LTE base stations, high-end radio frequency cards and military radar. Maximum transceiver data rates have been upped to 14.1Gb/s and density has been increased to 1.1 million logic elements, allowing support for the 16G Fibre Channel.
HardCopy V ASIC is a “low-risk” transceiver-based application-specific integrated circuit range with higher performance than older HardCopy devices. Additional logic and memory integration make allow this range to cater for multiple users, from low power, low cost devices to improved single-event upset tolerance while in production.
Chip giant Intel is to make semiconductors for a startup firm called Achronix Semiconductor.
Achronix said that Intel will build the FPGA (field programmable gate arrays) Speedster22i family using its 22 nanometre process technology.
The company designs FPGA semiconductors and claims that combining a 22 nanometre process will give its FPGAs 300 percent higher performance using 50 percent less power and with a 40 percent cost.
Intel does not normally take on a foundry role and it will be interesting to see how companies like TSMC and GlobalFoundries will react to the competition from the Santa Clara giant.
It isn’t the first time that Intel has built chips for other companies – in the 1990s it helped Hewlett Packard out by manufacturing PA Risc chips, while it still has to build Alpha processors – originally designed by DEC, in order to fulfil federal contracts that still have some years to run.
Intel still has to roll out its own semiconductors using 22 nanometre process technology, and hasn’t taken a stake in Achronix.