The module is fully compliant with the latest e-MMC standard, and has been designed for use in digital consumer products, including smartphones, tablet PCs and digital video cameras. Samples will be available in September, and mass production will start in the fourth quarter (October to December) of 2010.
The 128GB embedded device is said to integrate sixteen 64Gbit (equal to 8GB) NAND chips fabricated with Toshiba’s cutting-edge 32nm process technology and a dedicated controller into a small package 17 x 22 x 1.4mm. Toshiba claims it’s the first company to succeed in combining sixteen 64Gbit NAND chips, and applied advanced chip thinning and layering technologies to realise individual chips that are only 30 micrometres thick.
The company said that the device had been built due to growing demand for large density chips that support high-resolution video and deliver enhanced storage, particularly in the area of embedded memories with a controller function that minimises development requirements and eases integration into system designs.
The new device will be available from late this year.
And NAND, NAND, NAND: Macronix International Co has announced its 3D NAND Flash technology. The development is based on the company’s research results that found that its device provides a successful path to the most scalable and most efficient 3D NAND Flash using its own BE- SONOS (barrier engineering) charge-trapping technology and 3D decoding architecture.
In its paper, Macronix reports the fabrication and demonstration of an 8-layer, 75nm half-pitch, 3D VG (Vertical Gate) NAND Flash using a junction-free BE-SONOS device. The BE-SONOS charge-trapping device provides both high reliability and simple structure suitable for 3D. At an equivalent 0.0014 (um) 2 cell size, Macronix’s 3D VG NAND has shown no Z-directional interference, large read current, and large program window (7V) for MLC (Multi-level Cell) operation, it says.
C. Y. Lu, President of Macronix, said: “Traditional NAND Flash will be facing a technology barrier when it scales to below a 2Xnm node. The three-dimensional memory cell array structure has been proposed to be the most promising candidate for NAND Flash to shrink to below 1Xnm.”
The 3D cell technology stacks memory cells in three dimensions, making terabit NAND Flash possible. Using 3D stacking, NAND Flash may achieve higher data storage capacities and effectively lower fabrication cosst without relying on advances in lithography technology, which is why manufacturers are plonking cash into 3D.
Through detailed analyses on scalability, reading current (which determines read speed performance) and cross talk, Macronix’s work has chosen the VG architecture, believing it is the best approach. Simulation shows this structure could be scaled to 25nm node in a 3D array, providing density beyond conventional 2D NAND Flash.