Nvidia supercomputer building blocks revealed

While CES 2012 was at full blast and all eyes were centred on smart TV, smartphone and tablet goodies, details of Nvidia’s Echelon supercomputer chip have resurfaced a few weeks after Supercomputing 2011.

In the middle of 2010, Nvidia disclosed plans for a 20 Teraflop supercomputer named Echelon, within a competition set up by the US Department of Defense. It was competing head-on with Intel and IBM. Details of such a chip have been vague at best, but now some documents presented at Supercomputing 2011 have made their way to the public eye.

The slideware, obtained from a University of Gent presentation (PDF), shows off amongst other things, a block diagram for a 17mm-by-17mm chip (that’s 289mm2@10nm, by the way), packing  64×4 SM (streaming multiprocessor) attached to 4-way DRAM I/Os.

One can also see the core logic diagrams and SM Lane architecture (8 SM lanes per SM unit) detailed in the presentations.

Looking at the slides you can get the impression you’re actually looking at a GPU, which would be about right, but Nvidia is calling it a Network-on-Chip processor. We’d say it’s the internet in a server cabinet, as each chip will churn out 16 Teraflops (double-precision), and the company expects you to stick 128 of these in a cabinet for under 38kW of power.

Nvidia also estimates to be able to run these processors at a mild 2.5GHz frequency on a 10nm high-performance node, or 2GHz in the low-power version, and is aiming at 4x power savings over current 40nm designs.

Nvidia’s preferred foundry partner’s plans, TSMC, had previously announced that 10nm would be possible in the 2017/2018 time frame, at best, which is in line with the presentation projections.

Nvidia will face-off with Intel’s “Knights Landing” 2nd generation supercomputer chip in that time frame.

Pictures from PCInLife