Venray combines CPU and RAM

Designers at CPU outfit Venray Technology have emerged from their drawing board having come up with a chip that combines a CPU and DRAM.

The outfit claims that that there are shedloads of performance benefits by combining CPU and DRAM on to a single piece of silicon.

According to Hot Hardware who appears to have been giving Venray’s CTO Russell Fish a chinese burn until he spills the beans about the TOMI (Thread Optimized Multiprocessor) the idea is interesting, but barking.

The idea is supposed to solve a problem of scaling in modern microprocessors. This is caused by a gap between the CPU and DRAM clock speed and Instruction Level Parallelism which creates difficulty of decoding enough instructions per clock cycle to keep a core completely busy. Lastly, there is the problem that the faster a CPU is and the more cores it has, the more power it consumes.

TOMI attempts to fix he problem by using the same transistor structures as conventional DRAM and by trading clock speed and performance for ultra-low low leakage. Its design only uses a 22,000 transistor design, as compared to 30,000 transistors for the original ARM2.

Instead of surrounding a CPU core with a substantial amount of L2 and L3 cache, Venray stuck a CPU core directly into a DRAM design. So a TOMI Borealis core connects eight TOMI cores to a 1Gbit DRAM with a total of 16 ICs per 2GB DIMM.

This gives each DIMM 128 processor cores which are so small, such cores cost very little to build and consume only 23mW per core at 500MHz.

Hot Hardware seems to think that it is all too good to be true. It points out that Venray may have created a chip with power consumption an order of magnitude lower than anything ARM builds and more memory bandwidth than Intel’s highest-end Xeons, but it’s an ultra-specialised, ultra-lightweight core that ignores 25 years of flexibility to get more memory bandwidth.