Leading edge system-on-chip (SOC) designers are saying that their methods are changing dramatically.
Apparently the changes are completely different from the best practices of only a few years ago and the changes are proving painful for many architects, designers, and managers.
According to EDN, there is suddenly a dependence upon third-party IP (intellectual property). The complexity, especially in power and clock networks of power-managed designs, has forced changes in the design process. The new technology has influenced both front-and back-end design practices. It short it is giving them all a headache.
In the good old days it was possible to re-use IP and keep design teams small and all over the place. However now the systems are so complex that outfits are having a job assembling all the work. When designers encounter problems with integration the original IP developer is often the only one who can help.
Take for example Clock gating. This is a design step for reducing dynamic power nut it has made SOCs’ clock networks too complex.
Lisa Minwell, director of technical marketing at Virage Logic – taken over yesterday by Synopsys – said lots of these forces have combined not merely to make design more difficult, but also to change the approach.