Intel’s new 3D technology has got itself a rival.
SuVolta has released a transistor design that claims to cut power in half for fabs that adopt it.
The outfit is also working on circuit designs that could cut power for chip designers who use fabs with SuVolta’s transistors.
According to EETimes, the designs that SuVolta is coming up with could be a rival for Intel’s much touted 3D design.
Apparently the company has three executives who had some involvement in Intel’s pioneering 45 and 22nm process technologies.
Intel does have the advantage though. SuVolta has to work out a way of making its technology viable by selling its ideas to fabs. The fabs will then have to make the gear, something they may not be that keen on doing.
If they get away with it, SuVolta could start a whole new industry and give the outfit the ability to convince circuit designers they should adopt a whole new set of libraries to gain additional power reductions.
The company has built a 65nm SRAM device that is acting as a proof of concept. It also reports promising early test results at 28nm.
Fujitsu has announced that it will use the SuVolta technology in all its products and will ship the first chips using it sometime late next year. Broadcom and Cypress are also supposed to be snuffling around.
At the heart of SuVolta is a design for a junction field effect transistor (JFET) that can be applied to bulk CMOS to control voltage levels without cutting signalling speed. This makes it possible for reading and writing data at much lower voltages.
Apparently its SRAM, which is a 220 million gate device, managed acceptable yields in low volume production with all its modules working. It can read and write data at power levels as small as 0.42 of a volt. This is half of the power requirements of a modern SRAMs.