Shortly after Dadi Perlmutter had finished his keynote, much of which concerned Intel’s Sandy Bridge architecture, Intel held a briefing with Stephen S. Smith, VP; Opher Kahn, senior principal engineer; Tom Piazza, Intel Fellow and no square; and Bob Valentine, senior principal engineer. Sandy Bridge is pictured, left.
The integration of CPU, graphics, MC, PCI Express on a single chip required several challenges to be overcome including bandwidth, which gave rise to the ring interconnect concept.
Sandy Bridge contains a next gen Intel Turbo Boost feature, next gen graphics, an embedded display port, discrete graphics support, better performance, Intel’s advanced vector exension (AVX) an integrated memory controller with two channels of DDR3, and of course the never say die hyperthread technology.
The graphics shares the cache and the architects said that there were several pipeline features using the cache to lower latency in a lot of the operations.
Designing the process with integrated graphics means it’s hard to manage disparate teams of architects. Once the graphics is integrated on the same chip, the teams have to reconcile design and software and other features.
The system controller was built from scratch and PCI Express means connections to the IO are low latency and low power.
The ring architecture is very modular and it’s easy to replace two cores with multiple cores – Intel will do that in the future with the right die size and the right power for the different SKUs the company will release in the future.
Smith said that Intel has delivered five processors with Sandy Bridge coming in early 2011, while Ivy Bridge, on 22 nanometres is already being prepared in the Intel fabs.