Dubbed “Piton” after the metal spikes driven by rock climbers into mountainsides to aid in their ascent the chip was shown off at the Hot Chips conference.
The Princeton researchers designed their chip specifically for massive computing systems. Piton could substantially increase processing speed while slashing energy usage. The chip architecture is scalable — designs can be built that go from a dozen to several thousand cores.
The architecture enables thousands of chips to be connected into a single system containing millions of cores.
David Wentzlaff, a Princeton assistant professor of electrical engineering and associated faculty in the Department of Computer Science said that Piton was based on a new thinking about computer architecture. It was built specifically for data centers and the cloud.
“The chip we’ve made is among the largest chips ever built in academia and it shows how servers could run far more efficiently and cheaply.”
The current version of the Piton chip measures six millimetres by six millimetres and has 460 million transistors, each of which are as small as 32 nanometres.
The bulk of these transistors are contained in 25 cores. Most personal computer chips have four or eight cores.
In recent years companies and academic institutions have produced chips with many dozens of cores — but the readily scalable architecture of Piton can enable thousands of cores on a single chip with half a billion cores in the data centre, Wentzlaff said.
“What we have with Piton is really a prototype for future commercial server systems that could take advantage of a tremendous number of cores to speed up processing,” Wentzlaff said.
At a data centre, multiple users often run programs that rely on similar operations at the processor level. The Piton chip’s cores can recognise these instances and execute identical instructions consecutively, so that they flow one after another. Doing so can increase energy efficiency by about 20 percent compared to a standard core, the researchers said.
Piton chip parcels out when competing programs access computer memory that exists off of the chip so they do not clog the system. This approach can yield an 18 percent increase in performance compared to conventional means of allocation.
The Piton chip also gains efficiency by its cache memory management. In most designs, cache memory is shared across all of the chip’s cores. But when multiple cores access and modify the cache memory it is less efficient. Piton assigns areas of the cache and specific cores to dedicated applications. The researchers say the system can increase efficiency by 29 percent per chip.
Wentzlaff said. “We’re also happy to give out our design to the world as open source, which has long been commonplace for software, but is almost never done for hardware.”