Nvidia researcher says 450nm wafers are way overdue

A major problem for the IC industry is design process interaction and there are other problems associated with nodes less than 20 nanometres. That’s how John Chen, a senior research scientist at Nvidia, opened his keynote at IEF 2013.

He dubs the problems the three Ps – performance, perfection and precision. Each nanometre counts and every angstrom matters at the 20 nanometre level.  

Design Process Interaction means that each transistor at the sub 20nm level depends on its neighbours. Design rules become very complex and the rule book is torn up and that has an implication for yields.

There are three discontinues in 20 nm and beyond – the fist is FinFET. The second discontinuity is an economical one – the die cost and the yields you get from the wafer.  Die cost = F (scaling, wafer-cost(n) yield), where n is the process complexity factor because of the number of masking steps required.  When the n factor increases, the wafer costs increase.  The third discontinuity is the 450mm wafers which are overdue for the IC industry because that will reduce the die cost.

He believes that developments such as zero leakage transistors, III-V and Ge channel and carbon nanotubes will overcome the technology challenges the industry faces.

Chen studied quantum physics and of course now we’re really close to the boundaries of quantum physics in semiconductor manufacture. Chen has worked at Xerox PARC, TSMC and now Nvidia. He worked at Xerox Palo Alto research centrer in the mid 1980s and Alto was the first PC he worked on – Xerox also invented Ethernet, and VLSI technology.

In 1987 TSMC started and Chen worked there to service so called fabless companies and in every market segment the fabless firms represent a major force, he said.

Now Chen is at Nvidia and he believes the Nvidia Kepler 110 is one of the most advanced semiconductors on the planet, with 2048 cores on 28  nanometre technology.  It has 7.1 billion transistors and 20 kilometres of metal length.