Nvidia mocks Intel's HPC plans

Nvidia has been mocking Intel’s attempts to get into the high performance computing market.

Nvidia wants to rule the market with its Kepler-grade Tesla GPU while Chipzilla is investing its hopes with Knights Corner.

Nvidia’s chief technology officer of the Tesla business Steve Scott said that Intel’s marketing ignores how accelerator-based computing really works.

He said that for the last couple of years Intel has been telling would-be MIC users that its upcoming Knights Corner will deliver the performance of a GPU without having to adopt CUDA OpenCL, and as MIC architecture is x86-based, developing Knights Corner applications will not be that different than programming a multicore Xeon CPU.

But Scott has been pouring cold water on that. He said that porting applications for MIC, or even developing new ones, won’t be any easier than programming GPUs.

Writing in his bog he said there were lots of holes in Intel’s manycore story and its claims of superiority over GPU computing.

While he did not argue against the MIC as an accelerator, Scott said that HPC needs a hybrid (or heterogeneous) computing to move performance forward without consuming unreasonable amounts of electricity.

He said that traditional CPUs, whose cores are optimised for single-threaded performance, can’t handle work requiring lots of throughput. He said it was much better energy-wise to use simpler, slower, but more numerous cores.

Running throughput code on a serial processor sucks up too much energy, but running serial code on a throughput processor is just too slow.

He said that even if low single-threaded performance wasn’t a problem accelerators live on PCIe cards with limited amounts of memory which exist at the end of a PCIe bus.

If the software were to run on the accelerator, all its data and instructions would have to be shuttled in from main memory. This would create a bottleneck which would make everything slow down.

Scott said that hybrid computing needs to split the application intelligently between the CPU host and the accelerator.

Chipzilla has said little about application performance on the future MIC parts, and has not explained how that application split is going to work.