Moore's Law lives but silicon CMOS is doomed

While Intel is confident Moore’s Law will continue well into the future, an analyst has warned that tough times are ahead for silicon based CMOS devices.

Mike Bryant, CTO of analyst firm Future Horizons, said that there isn’t a reliable silicon transistor based 16 nanometre technology.  

He said leakage and other problems will make silicon based transistors too unreliable as the process continues to shrink. He said the properties of silicon limit the drive current to barely enough to drive the next gate.

While the industry may well solve that problem at a 16 nanometre process, Bryant said that the industry needs an alternative.

At 10 nanometres, said Bryant, Quantum Mechanics will overpower Newtonian physics. Unpredictable and variable “electron clouds” will have to be accounted for, with digital circuits fundamentally fault tolerant.

He quoted Niels Bohr’s (pictured, above left) observation: “Anyone who does not have a headache after first encountering quantum mechanics clearly has not understood a thing.”

But, Bryant observed, there are alternatives to silicon based CMOS. A strontium-germanium interlayer between a hi-k insulator and germanium channel will provide more generations. III-IV materials are less compatible with existing process technology.

He suggested that alternatives to Si CMOS include C60 nanotubes and graphene and diamond transistors.  He said that the carbon based benzene ring is likely to be the smallest switching building block, with a hexagon width of .28 nanometres and transistor size with gold contacts of around one nanometre.

3D transistor layers will rise on a single die, not a stacked die.

Nevertheless, he said the silicon wafer will be the base for multi-trillion element systems until nanobiotechnology replaces them. Whatever the future, quipped Bryant, computers on non silicon CMOS will probably still be running Microsoft Windows.

On 450mm wafers, Bryant said that developing equipment will cost $25 billion or so, a 450mm fab about $8 billion, and transition costs $100 billion. He said the likely date for a 450mm fab to come onstream is 2017, but that would be at the 11 nanometre process level.

There will be difficulties with EUVL lithography, and yields for non memory devices will be reduced at 450mm.

Only Intel, Samsung and TSMC have said they want to move to the larger wafer size – the rest of the industry is reluctant to make a move. The difficulty is the cost of making 450mm fabs can’t be paid for in terms of current profits.

Europe, he said, is concerned with semiconductor processing equipment and there;s rumours that there will be a 450mm pilot plant built in Crolles.  Intel, Samsung, and TSMC aren’t going to fund the cost of the move to the larger wafer size, and so governments may have to, Bryant suggested.