MIT 'Hornet' system simulates 1,000 core chip

With chip manufacturers looking to slap more cores on top of each other, researchers at MIT have developed a system that is even better at finding problems before a 1,000 core behemoth is built.

Even smartphones are getting the multicore treatment these days, but chip firms are reluctant to develop designs without a good inclination that it will work with 24 or 48 cores.

Researchers at MIT have now developed a software system which will give chip developers a much clearer idea of any potential problems that might crop up once they start building them.

The software simulator, named Hornet, is able to model chip performance much more accurately than other systems, with a greatly enhanced ability to find critical flaws in designs.

Traditionally, software simulations have struggled to deal with the sheer size of data that will be found in a chip with hundreds of cores, and would have to forsake accuracy in order to stay efficient.

When chip designers need greater accuracy, hardware simulation systems comprising of programmable chips that mimic multicore behaviour would be used.  However, hardware simulations are not as easy to configure for testing out alternative design proposals.

Hornet might not be as fast as other simulations, but it is able to provide a level of accuracy of the number of cycles a chip takes to complete a task.   According to the researchers, it has the ability to do so with great accuracy for up to 1,000 cores.

This allows Hornet to detect any inherent problems in a design, proving more adept than competing simulators at indentifying risks that others would miss, the researchers claim.