With the numbers of cores on a chip rising, designers could soon be looking to the internet for ways to improve communication speeds between cores.
Right now, there is an emphasis on adding more cores to the chip to increase computing speeds. Even smartphones are beginning to see quad cores burning a hole in your pocket.
With multi-core chips it is possible to achieve faster speeds because tasks can be split between a number of cores, giving advantages over a single core. With a small numbers of cores this presents little problems.
Communications between four, six or eight cores might be okay with a bus currently used on processors, problems can be encountered with processors using hundreds or thousands of cores in the future.
With a bus, only a pair of cores at a time are able to communicate directly, placing limits on speeds. There is a need for high end servers to add an extra bus once more than eight cores are strapped together. With the number of cores set to rise significantly, this causes problems – and the engineers say that continuing to add more and more buses won’t work.
For example, adding in a load of buses means that a system will require a lot more power.
According to the team, a potential answer is to follow the way information is passed around the web. This means communicating with other cores in the way that computers accessing the internet do, and forming the data being sent into packets.
Each chip would have its own router, and would be able to send information down a number of paths rather than just being tied to one core.
This would allow communication with the four nearest cores, allowing for lower voltage systems.
One of the problems with on chip networks is that when two packets arrive at one router, one has to wait in line while the other is processed. This could, in fact, slow processing down.
However, with ‘virtual bypassing’ sending a signal ahead to the router, the team reckons it can avoid packet gridlocks.
Using this router method, the researchers have conducted tests where they have reached close to the theoretical maximum speed for data transfer.
Another approach, known as low-swing signalling, involves a power reduction in the high and low voltages needed to create the ones and zeroes of a digital signal. Along with virtual bypassing, a test chip was able to achieve energy savings “orders of magnitude” that of a bus.