The 22 nanometer Ivy Bridge is a die shrink of the 32 nanometer Sandy Bridge, but it’s looking to be a big improvement, packing double the shaders and DirectX 11 support, along with a major boost to speed and bandwidth.
The key to Ivy Bridge’s possible success, according to SemiAccurate, is its stacked memory and silicon interposer.
Stacked memory is usually only employed on small, low-power devices, such as a smartphone, but Ivy Bridge is expected to pack low-power, low-speed, but large width memory of up to 512 bits.
It is believed that this will be LPDDR2 memory, possibly with a speed of only 1066MHz, and that memory stacking technology could bring it up to 1GB. This would give the Ivy Bridge a lead on bandwidth compared to anything else on the market.
The memory is then stacked upon a silicon interposer, a thin slate of silicon which is placed on top of the substrate but underneath everything else, a different modus operandi than the typical smartphone along with other mobile devices, where the memory is placed on top of the processor.
The reason a silicon interposer is essential for Ivy Bridge is the large width of the low-power memory. Since it will be much wider than that used in current Intel processors it brings with it the danger of excessively high pin and trace counts, which require more layers and, in turn, bump up the entire cost of the processor until it becomes completely unreasonable.
The silicon interposer solves this by allowing a thinner metal layer and tighter packing of the processor and memory chips, cutting down the required layers and reducing overall cost, which, when combined with the potential speed these processors can produce, may help the Ivy Bridge dominate the market.
The Ivy Bridge technology is expected to hit the shelves in late 2011 or early 2012, with the latter being more likely.