Intel, Samsung and Toshiba join to develop semiconductor technology

Intel will join forces with Toshiba and Samsung in order to halve semiconductor line width to nearly 10 nanometres by 2016.  

That’s’s scoop.

The three chipmaking firms will pool resources with the Japanese Ministry of Economy to develop technologies, basing their research and development at a public-private facility in Tsukuba, Ibaraki Prefecture.  The research will be focusing on technology for the semiconductor photolithography process which creates circuits on silicon wafers.

With the expectation that ultraviolet exposure devices will be ready to the reach the market by 2012 – allowing semiconductor circuit widths to be reduced to close to 10nm – the three corporations are keen to take full advantage of possible advancements with the assistance of 10 firms operating in semiconductor materials .

To actually mass produce at this width it will be necessary for the consortium to develop advancements in materials such as photoresist resins and photomasks, as well as equipment for chipmaking.

The research will offer the possibility to create 10nm-class NAND flash memory, and triple memory chips storage.  This will pave the way for a stamp-sized chip to hold 400 gigabytes, equivalent to approximately 100 high-definition movies.  For Intel the technology is likely to allow development of faster microprocessors.

The research and development will be funded partly by the Ministry of Economy, supplying 5bn Yen, and the consortium which will provide the remaining five billion yen of funding.  The joint venture will be the first time that foreign chipmakers are accepted by a Japanese public-private semiconductor development project.