Intel reveals more Ivy Bridge details

Intel has been telling the world and its dog about the good things that are under the bonnet of its coming Ivy Bridge chips.

Scott Siers, an Intel engineer, presented a paper on the chip to the assembled throngs at the International Solid-State Circuits Conference in San Francisco.

According to EE Times, Ivy Bridge, which will be the first processors to use Intel’s 22 nm tri-gate technology, will be released in four major variants.

Siers said that Ivy Bridge will have 20 channels of PCI Express Gen 3 interconnect and a Displayport controller and will be Intel’s first chip to integrate PCIe.

The first Ivy Bridge chip will head to desktops, notebooks, embedded and single-socket server systems with up to 8 Mbytes cache. It will integrate a memory controller and graphics, which have been upgraded to support DDR3L DRAMs and DirectX 11.0 graphics.

Siers said Intel spent a lot of time on the modularity of this die to create different flavours quickly.

The largest die will have four x86 cores and a large graphics block which can divided long its x- and/or y-axis using automated generation tools to create versions with two cores or a smaller graphics block.

Ivy Bridge will support low power 1.35V DDR3L and DDR power gating in standby and can handle up to 1,600 MTransfers/s as well as 1.5V DDR3.

There will be a new write assist cache circuit which provides a 100 millivolt power reduction.

Siers said that the Displayport block can run three simultaneous displays including one 1.6 GHz and two 2.7 GHz links.

The chip’s x86 CPU can run in data rates of 100 MHz while the graphics cores can manage 50 MHz increments. It can manage five power planes and 180 seperately gated clock islands.