Intel gives more info on Haswell

When Haswell launched last year Chipzilla kept very quiet about die sizes, transistor counts and almost anything surrounding the interface between Haswell and its optional embedded DRAM.

However, in the lead up to ISSCC, Intel has been filling in some of the details which we were lacking. At launch Intel only disclosed transistor counts and die areas for Haswell ULT GT3 (dual-core, on-die PCH, GT3 graphics) and Haswell GT2 (quad-core, no on-die PCH, GT2 graphics).

Now Intel has shown Anantech the minimum and maximum configurations for Haswell.The 4+3 Quad-Core T3e has die size of 260mm2 + 77mm2 and 1.7B transistors; The ULT 2+3 Dual-Core GT3 has a 181mm2 die 1.3B transistors.

The 4+2 Quad-Core GT2 has a die size of 177mm2 and 1.4BThe addition of a third graphics slice to a Haswell core accounts for around 300M transistors. That would put the ULT2+2 configuration at around 1B total transistors.Intel has also provided some additional information on the Crystalwell (embedded DRAM) design and configuration.

Intel explained how it arrived at the 128MB L4 eDRAM cache size, but is did not say the operating frequency of the memory or the interface between it and the main CPU die. Now it is saying that the 128MB eDRAM is divided among eight 16MB macros.

The eDRAM operates at 1.6GHz and connects to the outside world via a 4 x 16-bit wide on-package IO (OPIO) interface capable of up to 6.4GT/s. Haswell ULT variants use Intel’s on-package IO to connect the CPU/GPU island to an on-package PCH. In this configuration the OPIO delivers 4GB/s of bandwidth at 1pJ/bit.

When used as an interface to Crystalwell, the interface delivers up to 102GB/s at 1.22pJ/bit. That amounts to a little under 1.07W of power consumed to transmit/receive data at 102GB/s.

One of the things that Intel is keen on sharing now is how how it achieved power savings with Haswell, including using a new stacked power gate for the memory interface that reduced leakage by 100x over Ivy Bridge.

Haswell’s Full Integrated Voltage Regulator is a hot topic in Intel’s ISSCC papers. FIVR ends up being 90 per cent efficient under load and can enter/exit sleep in 0.32µs, requiring only 0.1µs to ramp up to turbo frequencies.