Cavium just released a family of OCTEON III MIPS64 multicore systems on a chip with anywhere from one to 48 cores that can produce more than 100Gbps of application performance per chip.
The design allows for linear scaling across multiple chips.
Syed Ali, President and CEO at Cavium, claims that the family can provide the most compute power of any standards-based communications processor chip, at 120GHz of 64-bit compute processing.
The OCTEON III can manage 4X higher application performance than the earlier OCTEON II with significantly superior performance per watt.
Ali claimed it was the industry’s first SoC to integrate search processing using Cavium’s NEURON Search processors along with DPI Acceleration.
This all means that next-generation networks can handle the explosive increase in traffic expected from the cloud and mobile broadband, as well as increased exchange of multimedia and video rich content.
Ali said that the higher traffic means that networks need intelligent application-aware and secure processing. This has shifted the bottleneck for L3 – L7 data and security services to CPU processing and means that there is shedloads of 64-bit CPU GHz processing power which needs to be done.
Cavium’s third generation custom cnMIPS “Real Cores” have up to 48 superscalar MIPS64 cores, operating at up to 2.5GHz, he added.
The new processor family can handle over 500Gbps of I/O connectivity per chip, over a variety of interfaces including multiple ports of 40G, 20G, 10G, GE, Interlaken, Interlaken/LA, SRIO, PCIe Gen3, SATA 6G and USB 3.0.
The first 28nm OCTEON III silicon is expected to sample in the second half of 2012.
*EyeSee We like the spec sheet. L2 Cache? “Large”.