Semi Alliance unites on common platform approach

The IBM Technology Alliance – which includes among its number GlobalFoundries (GloFo), ST Microelectronics, Samsung and Big Blue itself, said today that they will coordinate efforts to produce 28 nanometre semiconductors.

The alliance, which has been in existence for some years, has three other members, Renesas, Toshiba, and Infineon.

The four companies will develop standardised 28 nanometre process technology aimed at what they describe as the next generation of smart mobile devices. That technology will give faster processing speeds, smaller chips, lower standby power and longer battery life, the four partners said. Eventually, this technology, they said, will lead to a generation of portable electronics that can handle streaming video, data, voice and mobile commerce applications.

In practice, the 28 nano chips will use bulk CMOS and high-k metal gate processes, with members of the alliance all cooperating on what they describe as “Gate First” technology. The Common Platform has also collaborated with ARM and Synopsys ad have released common 28 nanometre circuits in their different fabs to allow for synchronisation. The first fab to complete the synchronisation will be later this year, and products will follow soon after.

Gary Patton, VP of IBM’s semiconductor R&D said that his company has a lot of experience synchronising multiple fabs, matching manufacturing specs to designs. “Our advanced technology can be implemented in many fabs around the world and produce the same results, providing clients with multiple suppliers for their product designs,” he said.

His sentiments were echoed by GloFo, ST Micro and Samsung, while ARM and Synopsys both applauded the move.

Malcolm Penn, CEO of Future Horizons, a UK semiconductor analyst company, told TechEye: “This is really only a scaled up version of Crolles alliance and is more important for the club members than the  industry/Intel as it gives them collective economy of scale.  Standardised process flows are increasingly required as the geometries scale due to transistor variability issues as well as operational logistic simplicity.  TSMC has already culled the number of variations it offers to essentially two at 28/32nm, never again we see the open field we saw at 65nm which brought them to their knees!

“As for Intel, it means nixie squat.  Their whole design methodology, cell libraries and process (gate last) is tuned to making processors not random logic. They get fabulous transistor densities but equally ‘fabulously’ high power dissipation. It really is chalk and cheese  This is part of the reason – apart from a complete cultural mind set disconnect – that they find logic so hard to make successful.

“Their (Intel’s) only hope as a logic fab/foundry would be to license/copy TSMC’s or the Club’s process and port it into their fabs, though this would need a separate fab and fab management concept.  If they used current practice they would either break their MCU fabs, as they would be switching between two wildly differing processes on such a regular basis something would go out of calibration, or they would (more likely) if they handed it to a potential customer drive the customer screaming and shouting back into the arms of TSMC.”